The "Digital Twin" Pedagogy
Unlike standard institutes, we use a "Digital Twin V-Model". Students must first master the design in TCAD simulation (Virtual Yield) and then validate it on physical wafers in our partner labs.
Course Tracks
1. VLSI Frontend Engineering (Logic & Verification)
- Advanced Design: RTL Design using Verilog/VHDL, FSM optimization, and Low-Power Design techniques.
- Verification Expert: Deep dive into SystemVerilog, UVM (Universal Verification Methodology), Assertion-Based Verification (SVA), and Coverage-Driven Verification.
- Project Work: Verification of AMBA AXI Protocols and RISC-V Cores.
2. VLSI Backend Engineering (Physical & Analog)
- Advanced Physical Design (PD): Netlist-to-GDSII flow, Floorplanning, Placement, CTS (Clock Tree Synthesis), Routing, and Sign-off (STA/IR Drop).
- Analog Layout Design: Custom layout for OpAmps, Bandgaps, and PLLs using FinFET/Planar technologies.
- Design for Test (DFT): Scan Insertion, ATPG, MBIST, and JTAG/Boundary Scan architectures.
3. Semiconductor Manufacturing Training
- Process Engineering: Hands-on training on Lithography (Mask Alignment), Thin Film Deposition (Sputtering/PECVD), and Wet Etching.
- Cleanroom Protocol: Certification in Hazardous Gas Handling, Safety Protocols, and Contamination Control.
